(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to methods used to create metal interconnect structures, and metal via structures, for semiconductor devices.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to decrease the processing costs of semiconductor chips. These objectives have been successfully addressed via micro-miniaturization, or the ability to fabricate semiconductor devices, comprised with sub-micron features. The sub-micron features allow performance degrading capacitances to be reduced. In addition the use of sub-micron features, allow smaller semiconductor chips to be obtained, however still possessing the same, or greater, device densities, as counterparts fabricated using larger features. This results in the attainment of more semiconductor chips, from a specific size, starting substrate, thus reducing the processing cost of the sub-micron, semiconductor chip.
The success of micro-miniaturization can be attributed to advances in specific semiconductor fabrication disciplines such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images in photoresist layers, to be routinely achieved. In addition the development of more advanced dry etching tools and processes, have allowed the sub-micron images, in masking photoresist layers, to be successfully transferred to underlying materials, used to fabricate semiconductor devices. However in addition to the contributions of advanced semiconductor disciplines, specific processing procedures, such as damascene, and dual damascene patterning, have been used to create, high aspect ratio, metal interconnect, and metal via structures, comprised with sub-micron features. However the damascene procedures, entailing forming the damascene, or dual damascene pattern, in. an insulator layer, followed by metal deposition, in the damascene opening, requires the use of "glue", or adhesive layers, permanently located, underlying the metal structures, formed in the damascene opening. The "glue" or adhesive layer, now part of the metal structure, increases the resistance of the metal structure, for a specific cross-sectional area.
This invention will teach semiconductor procedures needed to create high aspect ratio, metal interconnect structures, and metal via structures, using electro-plating, or electro-less plating, metal procedures, thus avoiding the need for "glue" or adhesive layers, used with the conventional metal filling of damascene openings. The metal interconnect, and metal via structures, formed via use of this invention, will use a disposable conductive layer, or seed layer, thus not adversely influencing the conductivity of the resulting metal structure. Prior art, such as Brighton et al, in U.S. Pat. No. 4,866,008, describe the formation of metal structures, via electroplating procedures, however the final metal structures include the underlying seed layers, which adversely influence the ability to obtain the desired conductivity, for the metal structures.